An Efficient Memory Architecture for Motion Estimation Processor Design

T h i s paper presents a novel m e m o r y arch i tec ture for motion e s t i m a t i o n processor design. By means of cond i t iona l select ion s t ra tegy , data i t e m s which can be reused are stored in m e m o r y banks and arranged i n a snakelike way. Both integer and half pixel motion vectors can be obtained b y the proposed architecture and an a r r a y processor, where m e m o r y bandwidth can be minimized and hence 1/0 pin-count can be reduced a lot. The proposed architecture is then demonstrated b y a test chip, whose hardware efficiency of processor elements is 100% when in teger motion vector is demanded.